1. Technical Field
The present disclosure relates to a semiconductor integrated circuit device and more particularly, to a layout configuration of an ESD (Electro Static Discharge) protection circuit (electrostatic discharge protection circuit) for protecting a circuit from being damaged due to electrostatic discharge.
2. Description of the Related Art
As shown in FIG. 15, in general, ESD protection circuits 51 and 52 are provided between signal terminal (input/output terminal) 53 and power supply terminal 54, and between signal terminal 53 and ground terminal 55, respectively. As the ESD protection circuit, various protection elements are used depending on purposes. Representative ones include a diode, a bipolar transistor, a MOS transistor, a thyristor, and the like.
FIG. 16 shows one example of a layout configuration of a conventional ESD protection circuit. Referring to FIG. 16, diode D serving as the protection element includes diffusion layers 65 as anodes, and diffusion layers 64 as cathodes arranged between them. Each of diffusion layers 64 and 65 is electrically connected to a wiring connected to an input/output terminal or the like, through contact holes 63 (Unexamined Japanese Patent Publication No. 2007-299790, FIG. 16).